1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly, to a method of isolating a first dielectric prior to formation of a second dielectric.
2. Description of the Relevant Art
Fabrication of metal oxide semiconductor (MOS) transistors is well known. The fabrication process begins by defining active areas on a semiconductor substrate where transistors will be formed. The active areas are isolated from each other on the semiconductor substrate by various isolation structures. Isolation structures come in many forms. For example, isolation structures can be formed by etching trenches into the substrate and filling them with a dielectric material. Isolation structures may also be formed by locally oxidizing the substrate using the well known LOCOS technique.
Once the isolation structures are defined between transistor active areas, a gate and insulating dielectric are formed. Typically, dielectric formation involves thermally oxidizing the silicon substrate by exposing the substrate to an oxygen bearing, heated ambient, in, for example, an oxidation furnace or a rapid thermal anneal (RTA) chamber. The oxygen reacts with the silicon substrate surface to form a thin layer of the dielectric (silicon dioxide) thereon. A gate conductor material is then deposited over the dielectric. Preferably, the gate is formed from polycrystalline silicon, or polysilicon. The polysilicon is then patterned using a photolithography mask.
An N-channel transistor, or N-MOS transistor, must in most instances be fabricated differently from a P-channel transistor, or P-MOS transistor. N-MOS transistors employ N-type dopants on opposite ends of the N-MOS gate conductor, whereas P-MOS transistors employ P-type dopants on opposite ends of the P-MOS transistor gate conductor. The regions of the substrate which receive dopants on opposite ends of the gate conductor are generally referred to as source/drain regions.
MOS transistors "turn on" and become active when appropriate voltages are applied to the gate (threshold voltage) and drain terminals. In the active state, the gate voltage creates an inversion layer or channel beneath the gate dielectric between the source/drain regions. Current conducts through this inversion layer. Often, the threshold voltage needed to create the inversion layer skews or drifts over time as will be more fully explained below.
Transistor speed and threshold voltage drift are factors affecting the design of most MOS transistors. One mechanism causing threshold voltage drift (threshold skew) relates to hot carrier effects (HCE), a phenomenon involving electric field acceleration of carriers (holes and electrons). The peak channel electric field, often referred to as the maximum field effect, occurs near the drain during normal transistor operation. The electric field near the drain causes primarily electrons in an n-channel transistor in the inversion layer to gain kinetic energy and become "hot." These hot electrons can be injected and become trapped in the gate oxide under appropriate transistor gate and drain bias voltage conditions. As a result, there is a net negative charge density in the gate dielectric, which can accumulate over time, resulting in a positive threshold voltage shift in N-MOS transistors. It is known that since hot electrons are more mobile than hot holes, HCE causes a greater threshold skew in N-MOS transistors than P-MOS transistors.
Transistor speed and HCE induced threshold voltage skew depend upon a variety of variables including (1) gate dielectric thickness, (2) gate dielectric material, and (3) gate voltage. Thinner gate dielectrics result in faster transistors but produce greater skew in threshold voltage due to HCE for a constant operating voltage. Dielectrics formed from a material which retard hot carrier injection reduce threshold voltage skew but often produce transistors which may be slower than those with gate dielectrics formed solely from silicon oxide. Lastly, higher voltages applied to the gate increase transistor speed but produce greater HCE threshold voltage skew.
It is desirable to fabricate each transistor within an integrated circuit with respect to individual parameters thereby maximizing transistor speed and minimizing HCE induced threshold voltage skew. Transistors in an integrated circuit are often contained in peripheral devices, such as translators or buffers, or in core devices, such as RAM, ROM, or circuitry. To increase overall integrated circuit speed and reliability there is a need to design gate dielectrics of core transistors differently than gate dielectrics of peripheral transistors. For example, core transistors can be made to operate faster at lower gate voltages by designing core transistors with thinner dielectrics. Peripheral transistors can be designed to withstand threshold voltage skew by making their gate dielectrics thicker.
The prior art provides a multi-step process for growing core and peripheral transistor gate dielectrics with different thicknesses. The prior art technique is described below in connection with FIGS. 1-8.
In particular, FIG. 1 shows a cross-sectional view of a wafer having a silicon substrate 10 with a first dielectric layer 12 formed thereon by subjecting, for example, silicon substrate 10 to a heated ambient containing oxygen.
FIG. 2 shows a layer of photoresist 14 formed over first dielectric layer 12. The photoresist is selectively exposed to light transmitted through a photomask plate (not shown) having opaque and light transmissive regions. Regions of the photoresist 14 exposed by photomask transmitted light are removed by subjecting the wafer to standard washing techniques. FIG. 3 shows the result of selectively exposing and removing regions of the photoresist.
The wafer is then subjected to an etching technique which removes those regions of the first dielectric 12 left unprotected by photoresist 14. The etching results are shown in FIG. 4 which exhibits a small portion of dielectric 12 aligned with a small portion of photoresist 14.
A second dielectric can be formed by again subjecting the wafer to a heated ambient containing oxygen. The oxygen reacts with those portions of the silicon substrate exposed by the prior etching step. However, before the second dielectric can be formed, the photoresist covering first dielectric 12 must be removed. This is because photoresist is a carbon based material, and if the photoresist is not removed prior to the second dielectric forming step, the photoresist will react in the high temperature oxygen ambient, the product of which will inadvertently diffuse to and contaminate the exposed surface area's wafer where the formation of the second dielectric is to occur.
FIG. 5 shows example results of removing the photoresist 14 covering dielectric 12. The photoresist removal technique occasionally does not totally remove all the photoresist material. It has been shown that the removal technique may inadvertently leave behind bits and pieces of photoresist on the surface of the dielectric 12. FIG. 5 shows an example of a residual portion 16 of a photoresist on dielectric 12 remaining after the photoresist removal.
After the photoresist removal step, as noted above, the wafer is subjected to the heated oxygen ambient to form second dielectric 20. See FIG. 6. In addition to reacting with the exposed silicon, the ambient oxygen additionally diffuses through first dielectric 12 and reacts with the silicon substrate 10 underlying the dielectric 12 thereby causing further growth of first dielectric 12. The results of forming the second dielectric 20 and further growing the first dielectric 12 is shown in FIG. 6. As can be seen, the two dielectrics have different thicknesses t.sub.1 and t.sub.2. Unfortunately, dielectric 12 is not uniform in thickness due to the presence of the residual photoresist 16. More particularly, the residual photoresist material 16 blocks diffusion of ambient oxygen through dielectric 12 underlying the residual photoresist material. As a result, the area of dielectric 12 underneath the residual photoresist material 16 cannot further grow resulting in a gap 18 as shown.
FIG. 7 shows a cross-sectional view of the wafer with a polysilicon layer 22 over both the first and second dielectrics 12 and 20. The polysilicon layer 22 is then selectively exposed and developed gate structures 24 as shown in FIG. 8.
The resulting gate structures 24 and dielectrics 12 and 20 ideally support remotely positioned transistors 26 and 28 (see FIG. 8) in peripheral and core devices respectively. Dielectric 12 of peripheral transistor 26 generally has a greater thickness ti when compared to the thickness t.sub.2 of the dielectric 20 of core transistor 28. As such the peripheral transistor can be operated with a higher gate voltage thereby reducing threshold voltage skew created by HCE. The core transistor by virtue of its thinner dielectric 20, can be operated with a lower gate voltage which in turn reduces threshold voltage skew caused by HCE while maintaining a relatively high operational speed.
A problem, however, arises due to the residual photoresist. As can be seen in FIG. 8, the gate 24 extends into the gap 18 of dielectric 12 created by the residual photoresist 16. As a result, dielectric 12 experiences an increased electric field at that area of reduced dielectric thickness when a voltage is applied to gate 24. The increased electric field creates a greater risk that dielectric 12 will rupture at gap 18. In other words, the gap created by the residual photoresist increases the likelihood of transistor failure due to dielectric rupture. This problem is compounded by the fact that dielectric 12 is subjected to the higher gate voltages associated with peripheral devices.
The problems created by residual photoresist described above also arise during formation of single dielectrics in a device having dual thicknesses. Many modern programmable devices, including EEPROMs, may be defined by sophisticated structures having a single dielectric with multiple thicknesses. FIG. 9, for example, shows a cross-sectional view of an EEPROM having a multi-thick dielectric 30 along with program transistor 32, a buried control gate 34, a floating gate 36, a sense transistor 38, and a read transistor 40. The multi-thick dielectric 30 includes a tunnel dielectric 42 and a gate dielectric 44. Proper operation of the EEPROM requires the tunnel dielectric 42 to be significantly thinner when compared to the thickness of gate dielectric 44 for the following reasons.
The EEPROM shown in FIG. 9 can be "erased" or "programmed" by injection or removal of electrons onto floating gate 36. In the "erase" mode, high voltage is connected to both the buried control gate 34 and gate 46 of program transistor 32. Concurrently, a low voltage (ground, for example) is applied to source 48 of program transistor 32. Thus biased, a strong electric field is induced across tunnel dielectric 42 between floating gate 36 and drain 50 of program transistor 32. This strong electric field induces electrons to tunnel from drain 50 to floating gate 32 causing an accumulation of negative charge thereon. Since the floating gate 36 also acts as the gate which controls sense transistor 38, the accumulation of negative charge raises the threshold voltage of sense transistor 38 which, in turn, inhibits current flow therethrough during a subsequent "read" mode. In the program mode, the control gate 34 and the source 48 of program transistor 32 are reversed biased while program transistor is activated thereby creating a strong reverse electric field across tunnel dielectric 42. The reverse bias removes the electrons from floating gate 36 by a tunneling mechanism. The removal of the electrons lowers the threshold voltage of associated sense transistor 38 which, in turn, promotes, current flow therethrough during a subsequent "read" mode.
To achieve electron tunneling through tunnel dielectric 42 in the presence of a strong electric field, it is imperative that tunnel dielectric 42 have a relatively thin cross-sectional thickness when compared to the thickness of gate dielectric 44. Typically, a high quality EEPROM can be manufactured with tunnel dielectric 42 having a thickness of 80-100 angstroms.
Prior art techniques for forming tunnel and gate dielectrics in EEPROMs require multiple steps. The prior art technique will now be described with reference to FIGS. 10-17 which show region A of the EEPROM in FIG. 9 after successive processing steps. More particularly, FIG. 10 shows wafer having a silicon substrate 60 with a thin layer of dielectric 44 formed thereon. The dielectric may be formed by reacting the surface of silicon wafer 60 with a heated ambient containing oxygen.
Thereafter, the dielectric 44 is covered with a layer of light sensitive photoresist 62 as shown in FIG. 11. The photoresist is then selectively exposed to light transmitted through a photomask plate (not shown) having opaque and light transmissive regions. Light exposed regions of the photoresist 62 are removed by subjecting the wafer to a washing technique. FIG. 12 shows the result of the exposing and removing steps to create a window 64 through photoresist 62 to expose dielectric 44.
The wafer is then subjected to an etching technique which removes regions of dielectric 44 exposed by window 64, the results of which are shown in FIG. 13. This provides an area on the silicon substrate surface where tunnel dielectric 42 can be grown. Before the tunnel dielectric 42 can be formed, the photoresist material 62 must be removed since photoresist is formed from a carbon-based material and will react in the high temperature oxygen containing environment needed to form the tunnel dielectric, the product of which will inadvertently diffuse into the exposed surface of the substrate area and preclude any formation of tunnel dielectric thereon.
The photoresist removal technique occasionally does not remove all of the photoresist material. It has been shown the removal technique may inadvertently leave behind bits and pieces of photoresist on the surface of the wafer. FIG. 14 shows examples 66 of residual photoresist particles remaining on the surface of dielectric 44 after photoresist removal.
After photoresist removal, the wafer is subjected to a second dielectric formation step to form the tunnel dielectric 42 on the exposed area. In this step, like the step for forming the gate dielectric 44, the tunnel dielectric 42 is formed by subjecting the wafer to an ambient containing oxygen at elevated temperatures. In addition to reacting with the exposed silicon substrate, the ambient oxygen diffuses through gate dielectric 44 and reacts with the silicon thereunder resulting in further growth the gate dielectric 44. FIG. 15 shows the results of the formation of the tunnel dielectric 42 and the further growth of gate dielectric 44. However, as can be seen in FIG. 15, the resulting thickness t.sub.1 of gate dielectric 44 is non-uniform due to gaps 68 created by the presence of photoresist particles 66 inadvertently remaining after the photoresist removal step. The particles 66 inhibit diffusion of oxygen through gate dielectric 44 during the second oxidation step. Accordingly, the silicon beneath the particles 66 cannot react with oxygen and cause further growth of gate dielectric 44.
FIGS. 16 and 17 show the results of depositing polysilicon and selective etching thereof to form floating gate 36 and gate 46 of program transistor 32.
As can be seen in FIG. 17, gate 46 extends into gate dielectric 44 due to the gaps 68. In operation, gate 46 is subjected to high voltages during the "programming" and "erasing" of the EEPROM. These voltages produce an electric field across gate dielectric 44, which is directly proportional to the inverse of the thickness of the underlying gate dielectric. During the "programming" and "erasing" modes, gate dielectric 44 is subjected to an unanticipated high electric field at areas of reduced thickness (i.e., the gaps 68 created due to the residual photoresist). These high electric fields may cause the dielectric to break down or rupture which in turn may render program transistor 32 inoperable.